Risc V GitHub Repositories

Parsing gigabytes of JSON per second : used by Facebook/Meta Velox, the Node.js runtime, ClickHouse, WatermelonDB, Apache Doris, Milvus, StarRocks

Speech-to-text, text-to-speech, speaker diarization, speech enhancement, source separation, and VAD using next-gen Kaldi with onnxruntime without Internet connection. Support embedded systems, Android, iOS, HarmonyOS, Raspberry Pi, RISC-V, RK NPU, Axera NPU, Ascend NPU, x86_64 servers, websocket server/client, support 12 programming languages

A FREE comprehensive reverse engineering tutorial covering x86, x64, 32-bit/64-bit ARM, 8-bit AVR and 32-bit RISC-V architectures.

RT-Thread is an open source IoT Real-Time Operating System (RTOS). https://rt-thread.github.io/rt-thread/

Your Gateway to Embedded Software Development Excellence :alien:

Open-source high-performance RISC-V processor

A secure embedded operating system for microcontrollers

Lightweight justice for your single-board computer!

面向IoT领域的、高可伸缩的物联网操作系统，可去官网了解更多信息https://www.aliyun.com/product/aliosthings

OS kernel labs based on Rust/C Lang & RISC-V 64/X86-32

A fully compliant RISC-V computer made inside the game Terraria

Modern, secure, portable, multiprotocol bootloader and boot manager.

A graphical processor simulator and assembly editor for the RISC-V ISA

The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configurations are capable of booting Linux.

Raspberry Pi Pico Arduino core, for all RP2040 and RP2350 boards

The official repository for the gem5 computer-system architecture simulator.

Renode - Antmicro's open source simulation and virtual development framework for complex embedded systems

Reko is a binary decompiler.

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

RISC Zero is a zero-knowledge verifiable general computing platform based on zk-STARKs and the RISC-V microarchitecture.

Let's write an OS which can run on RISC-V in Rust from scratch!

iPXE network bootloader

Ibex is a small 32-bit RISC-V CPU core with high-level of verification (previously known as zero-riscy)

All CPU and MCU documentation in one place

Unicode routines (UTF8, UTF16, UTF32) and Base64: billions of characters per second using SSE2, AVX2, NEON, AVX-512, RISC-V Vector Extension, LoongArch64, POWER. Part of Node.js, WebKit/Safari, Ladybird, Chromium, Cloudflare Workers, Ghostty and Bun.

Fast, modern C++ DSP framework, FFT, Sample Rate Conversion, FIR/IIR/Biquad Filters (SSE, AVX, AVX-512, ARM NEON, RISC-V RVV)

Run a 1-billion parameter LLM on a $10 board with 256MB RAM

The Ultra-Low Power RISC-V Core