Digital Design GitHub Repositories

📚 📖 📚CSE GATE Resources for GATE and CSE Aspirants 😎 😁 . Show your ❤️ by ⭐️⭐️

Teaching Materials for Dr. Waleed A. Yousef

ASIC implementation flow infrastructure, successor to OpenLane

Master AI inference, AI agent harness systems, and hardware engineering — then design a physical AI chip. That is the goal.

This repository hosts the code for an FPGA based accelerator for convolutional neural networks

Educational RV32I FPGA CPU/SoC project organized for JYD RISC-V contest-style Vivado reconstruction and verification.

Python script for generating lookup tables for the gm/ID design methodology and much more ...

A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.

Open-source FPGA development board for education and digital design learning. Designed for accessibility, reproducibility and seamless integration with open FPGA toolchains for students, makers and academic environments.

Comprehensive verification suite for the AHB2APB Bridge design, featuring SystemVerilog and UVM-based methodologies. 🌉🚀

Introduction to FPGA emulation and digital design. This capstone project was part of the 2021 University of San Diego Shiley-Marcos School of Engineering & Computing Showcase.

Educational materials and tooling for digital HDL synthesis in Python with myHDL

An open source, parameterized SystemVerilog digital hardware IP library

Minimalistic RV32I RISC-V Processor in System Verilog

A minimalistic single-cycle RISC-V platform for demonstrational and educational purposes in Logisim Evolution.

VHDL code examples for a digital design course

Verilog miniRV/RISC-V style CPU course project featuring single-cycle and five-stage pipeline designs with hazard handling.

Solutions for The Nand Game, a game that teaches the fundamentals of computing by building a computer from scratch.

AdobeAllInOne is a comprehensive suite of creative software tools developed by Adobe. It includes a range of applications for design, photography, video editing, and more, making it the ultimate solution for all your creative needs.

32 bit pipelined binary floating point adder using IEEE-754 Single Precision Format in Verilog

This Repository contains the Implementation of the AMBA APB4 Protocol with Verilog, featuring an APB master, APB slave with cache memory, and comprehensive testbenches. Includes scripts for fast simulation and synthesis using QuestaSim, Vivado and Quartus Prime

An experimental HDL simulator written in Common Lisp focused on interactive and extensible hardware design and verification.

A collection of my cources, lectures, articles and presentations

Distributed arithmetic (DA) is another way of implementing a dot product where one of the arrays has constant elements. The DA can be effectively used to implement FIR, IIR and FFT type.The DA logic replaces the MAC operation of convolution summation o into a bit-serial look-up table read and addition operation .

A VHDL-based VGA driver to display 256 different colors on a monitor.

A repository containing the source codes for the Digital Design and Computer Organization Laboratory course (UE18CS2) at PES University.

An introduction to integrated circuit design with Verilog and the Papilio Pro development board.

Router 1 x 3 verilog implementation

UVM-based functional verification of an APB-based UART Master Core RTL. Includes multi-agent environment, assertions, coverage collection, and multiple test scenarios (full/half duplex, parity, framing, timeout errors) achieving 100% functional coverage and protocol compliance.

SystemVerilog examples for a digital design course