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PicoRV32 - A Size-Optimized RISC-V CPU

Verilog Ethernet components for FPGA implementation

OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

Open source FPGA-based NIC and platform for in-network compute

No repository description provided.

RTL, Cmodel, and testbench for NVDLA

Verilog AXI components for FPGA implementation

IC design and development should be faster，simpler and more reliable

Must-have verilog systemverilog modules

HDL libraries and projects

The Ultra-Low Power RISC-V Core

SERV - The SErial RISC-V CPU

FPGA modules used together with the PCILeech Direct Memory Access (DMA) Attack Software

RISC-V CPU Core (RV32IM)

Verilog PCI express components

A small, light weight, RISC CPU soft core

OpenXuantie - OpenC910 Core

An open source GPU based off of the AMD Southern Islands ISA.

A minimal tensor processing unit (TPU), inspired by Google's TPU V2 and V1

Full-throttle, wire-speed hardware implementation of Wireguard VPN, using low-cost Artix7 FPGA with opensource toolchain. If you seek security and privacy, nothing is private in our codebase. Our door is wide open for backdoor scrutiny, be it related to RTL, embedded, build, bitstream or any other aspect of design and delivery package. Bujrum!

32-bit Superscalar RISC-V CPU

The USRP™ Hardware Driver Repository

Source and Documentation files for USB C Industrial Camera Project, This repo contains PCB boards, FPGA , Camera and USB along with FPGA Firmware and USB Controller Firmware source.

An Open-source FPGA IP Generator

RISC-V XV6/Linux SoC, marchID: 0x2b, 0x34

3-stage RV32IMACZb* processor with debug

High performance motor control

MNT VA2000, an Open Source Amiga 2/3/4000 Graphics Card (Zorro II/III), written in Verilog

An FPGA-based Field Oriented Control (FOC) for driving BLDC/PMSM motor. 基于FPGA的FOC控制器，用于驱动BLDC/PMSM电机。