GitHub Trending Bluespec

Boilerplate codebase for Embedded FPGA kernel development via YosysHQ & BSV

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A library of specific implementations of cheri and providing an abstract interface to those implementations

A Bluespec SystemVerilog library of miscellaneous components

Textbook and full source codes to learn basics of RISC-V pipelined CPU design using the Bluespec Hardware Design Language(s)

Identify rogue taxa in phylogenetic trees within R

Development area for another repo: Learn_Bluespec_and_RISCV_Design

Direct Memory Access Controller and Memory Interface

Quint specification of Mysticeti Consensus

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Multi-level tag controller for emulating a tagged memory using an in-memory table.

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A place to share libraries and utilities that don't belong in the core bsc repo

RISC-V BSV Specification

Boilerplate codebase for AMD FPGA kernel development via BSV

P4-14/16 Bluespec Compiler

RoCEv2 hardware implementation in Bluespec SystemVerilog

Hardware implementation of an OmniXtend Memory Endpoint/Lowest Point of Coherence.

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MonadBFT formal specification in Quint

Manythread RISC-V overlay for FPGA clusters

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A Quint specification of Tendermint consensus, based on the paper

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Bluespec environment for working with the ulx3s board and its lattice ecp5 fpga

Miscellaneous components for bluespec

Greenland ice borehole temperature profiles