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A minimal GPU design in Verilog to learn how GPUs work from the ground up

Verilator open-source SystemVerilog simulator and lint system

OpenTitan: Open source silicon root of trust

Ibex is a small 32-bit RISC-V CPU core with high-level of verification (previously known as zero-riscy)

Official repository of the AWS EC2 FPGA Hardware and Software Development Kit

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

A Verilog synthesis flow for Minecraft redstone circuits

OpenSource GPU, in Verilog, loosely based on RISC-V ISA

Send video/audio over HDMI on an FPGA

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

RSD: RISC-V Out-of-Order Superscalar Processor

SCR1 is a high-quality open-source RISC-V MCU core in Verilog

VeeR EH1 core

AXI, AXI stream, Ethernet, and PCIe components in System Verilog

A Linux-capable RISC-V multicore for and by the world

Project F brings FPGAs to life with exciting open-source designs you can build on.

Common SystemVerilog components

Proving leftpad correct two-dozen different ways

BaseJump STL: A Standard Template Library for SystemVerilog

Contains the code examples from The UVM Primer Book sorted by chapters.

Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.

NonTrivial-MIPS is a synthesizable superscalar MIPS processor with branch prediction and FPU support, and it is capable of booting linux.

The root repo for lowRISC project and FPGA demos.

CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches, BP, FPU, VM/MMU, AHB, RAMs, and peripherals.

This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain accelerated by a PULP cluster with 8 cores.

This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no cluster.

AMBA AXI VIP

training labs and examples

Baochip 1x Silicon

Verilog evaluation benchmark for large language model